Model & package intelligence
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TECH PUBLIC AZ5325-01F AZ5325
Configuration
1 options
Configuration
26+
Available for RFQ
Technical data
Product details
19
specifications
Core information
- Product name
- TECH PUBLIC AZ5325-01F
- Type
- TECH PUBLIC
- Minimum package
- 10000 圆盘
Technical parameters
- Electronic Component
- Electronic Component
- Electronic Component
- TECH PUBLIC
- Electronic Component
- AZ5325-01F
- Electronic Component
- 1
- Package
- DFN1006-2
- Electronic Component
- Electronic Component
- Electronic Component
- ESD and Surge Protection (TVS / ESD)
- Electronic Component
- 0.009g
- Electronic Component
- 1
- Channel Count
- Electronic Component
- Cj- Capacitor
- 0.6pF
- Electronic Component
- BM0226539321
- Voltage
- 9V；15V
- Electronic Component
- IEC 61000-4-5；IEC 61000-4-2
- Current(Ir)
- 80nA
- Voltage(VBR)
- 9V
For datasheets, package documents, compatible-part guidance, or other technical resources, contact WMSIC customer service. Availability is confirmed case by case.
AZ5325-01F 产品概述
一、简介
AZ5325-01F 是 TECH PUBLIC（台舟电子）推出的一款小尺寸单路双向 TVS/ESD 晶片，用于静电放电与浪涌保护。器件采用 DFN1006-2 微型封装，专为对空间、带宽和低漏电有高要求的便携、通信和工业电子接口设计，满足 IEC 61000-4-2（ESD）与 IEC 61000-4-5（浪涌）防护等级要求。
二、主要特性
- 极性：双向，适合保护双向信号线或对称接口。
- 通道数：单路（单条信号线保护）。
- 反向截止电压 (Vrwm)：5V，适配 5V 或以下工作电压系统（如 USB、GPIO 等）。
- 击穿电压 (Vbr)：约 9V。
- 钳位电压 (Vc)：在不同冲击条件下钳位电压为 9V（小冲击）至 15V（大浪涌），能在过压瞬态时有效限制电压峰值。
- 结电容 (Cj)：典型 0.6 pF，极低电容对高速差分或单端信号影响小。
- 反向电流 (Ir)：典型 80 nA，低漏电利于电池供电与低功耗系统。
- 封装：DFN1006-2（小型、易于贴装，利于高密度布局）。
三、典型应用
- USB/OTG、串行接口（UART、SPI、I2C）和 GPIO 线路保护。
- 手机、平板、笔记本等便携设备的外部接口保护。
- 工业控制与IoT终端的信号线静电及浪涌防护。
- 摄像头、传感器线路与其他对电容敏感的高速接口。
四、主要电气参数（要点）
- Vrwm：5V
- Vbr（击穿）：≈9V
- Vc（钳位）：约 9V（小冲击）至 15V（大浪涌，随冲击电流增大）
- Cj：0.6 pF（典型）
- Ir：80 nA（典型）
- 标准兼容：IEC 61000-4-2 / IEC 61000-4-5
注：实际钳位电压受测试条件（如峰值冲击电流、波形）影响，选型时应参考完整的器件数据手册及典型测试曲线。
五、封装与安装建议
- DFN1006-2 封装适合自动贴片生产，面积小、厚度低。
- 布局建议：器件应尽量靠近被保护的连接器或引脚放置，外露焊盘朝向接地或信号返回路径，走线短且宽。对于外部接口，建议在 TVS 与接地之间使用至少一条接地过孔以降低回路电感。
- 温升与焊接：小封装在大能量浪涌时有局部温升风险，若系统可能经历高能浪涌，应做热仿真或并联更大功率的浪涌保护元件。
六、选型与可靠性提示
- 若主工作电压稳定在 5V 以下，AZ5325-01F 是良好选择；对更高工作电压需确认 Vrwm 与系统余量。
- 关注钳位电压在最大浪涌条件下是否对后端电路安全；必要时与系列更高功率 TVS 或配合熔断/限流元件使用。
- 在高速数据信号上使用时，0.6 pF 的低结电容可最大限度降低信号失真，但仍建议在样机阶段做信号完整性验证。
如需器件完整数据手册、典型波形或参考设计图，请告知使用场景与系统要求，我可以提供更具体的选型与布局建议。
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